Recently, television receivers, which use digital signal processing systems, have been developed. A specialized reproduction function which uses digital memories such as still picture reproduction can be simply achieved by constructing a television receiver with a digital signal processing system.
Among the types of digital television receivers, there are those which adopt a clock fH phase-synchronized with the horizontal synchronization signal and those which adopt a clock fsc phase-synchronized with the burst signal, which is a reference for the color subcarrier, as the system clock. When a clock fsc phase-synchronized with the burst signal is used, in the case of color demodulation, the B-Y and R-Y color difference signals can be demodulated by latching the color component to timing synchronized to the clock. Thus, a simple construction of the color demodulation circuit is achieved.
However having the case of a VCR (Video Tape Recorder), in image signals, which contain jitter, the color subcarrier frequency and the horizontal synchronization signal frequency diverge from an interleaved relationship. That is to say, in this case, if clock fsc is adopted, the sampling point of the horizontal synchronization signal is not constant, and the horizontal output pulse is bound to have jitter. For this reason, there is a disadvantage in that the amount of digital data in one horizontal period or one vertical period will not be constant.
Therefore, this type of case requires the adoption of the clock EH type system. However, in the NTSC and PAL systems, a color subcarrier is required in order to execute synchronized demodulation of the AM-modulated signals. For this reason, the design is such that a clock phase-synchronized with the color subcarrier is demodulated by the clock fH.
FIG. 1 is a block diagram showing a prior art color subcarrier demodulation circuit which generates clock fH and, at the same time, demodulates the color subcarrier using this clock fH.
The analog video signal input through input terminal 1 is supplied to A/D converter 2. A/D converter 2 samples the input analog video signal at a clock rate with frequency nfH (hereafter, clock nfH) from waveform shaping circuit 12 (described below), and converts it to a digital signal. The digitized video signal is supplied to horizontal synchronization signal separation circuit 3. Horizontal synchronization signal separation circuit 3 separates the horizontal synchronization signal from the digital video signal and supplies it to phase comparator 4. At the same time, frequency divider circuit 5 divides clock nfH from waveform shaping circuit 12 by n and supplies a signal with frequency fH to phase comparator 4. Phase comparator 4 compares the phases of the two inputs and outputs a phase error signal to loop filter 6. The phase error signal is integrated by a specified time constant in loop filter 6 and is output as control signal CH for digital oscillator 7. A clock of frequency fx is also supplied from crystal oscillator 8 to digital oscillator 7.
FIG. 2 is a circuit diagram showing a practical construction of digital oscillator 7, and FIG. 3 is a waveform diagram illustrating its operation.
Control signal CH is input from loop filter 6 to digital oscillator 7 via input terminal 21. The m1 bit adder 22 adds the output of data flip-flop (hereafter, DFF) 23 and control signal CH and outputs this to DFF 23. DFF 23 supplies the output of adder 22 to adder 22 at a clock of frequency fx which is input via terminal 24. That is to say, control signal CH is cumulatively integrated at every clock cycle by adder 22 and DFF 23. As shown in FIG. 3, a sampled saw-tooth wave with an amplitude of two (2) powered by m1 sampled at a cycle of 1/fx appears at output terminal 25. Since the oscillation frequency f1 of this saw-tooth wave is regulated by the cycle of 1 sample being 1/fx, it can be expressed by the following Equation (1). EQU f1=(CH/2.sup.m1).multidot.fx (1)
As shown by Equation (1), the output of digital oscillator 7 is proportional to control signal CH, the phase error signal from phase comparator 4. The output signal of digital oscillator 7 is converted from a saw-tooth wave to a sine-wave in sine-wave converter (hereafter referred to SIN converter) 9. It is then converted to an analog signal by D/A converter 10, and is supplied to low-pass filter (referred to as LPF, hereafter) 11. LPF 11 eliminates the feed-back component of the input analog signal then supplies the input analog signal to waveform shaping circuit 12. Waveform shaping circuit 12 shapes the waveform of the output of LPF 11 to a binary digital signal. The output clock of waveform shaping circuit 12 is divided into 1/n by frequency divider circuit 5 and is fed back to phase comparator 4. That is to say, a phase-locked loop (PLL) is composed of phase comparator 4, loop filter 6, digital oscillator 7, SIN converter 9, D/A converter 10, LPF 11, waveform shaping circuit 12 and frequency divider circuit 5. A clock nfH of frequency n times is output from waveform shaping circuit 12 by phase-synchronization with the horizontal synchronization signal from horizontal synchronization signal separation circuit 3.
At the same time, the digital video signal from A/D converter 2 is also supplied to burst separator circuit 13. Burst separator circuit 13 extracts the burst signal, which is the reference of the color subcarrier and outputs this to phase comparator 14. Phase comparator 14 compares the phases of the extracted burst signal and the output signal of SIN converter 17 (described below) and supplies a phase error signal to loop filter 15. Loop filter 15 integrates the phase error signal by a specified time constant and outputs the integrated phase error signal as control signal CS for digital oscillator 16. Digital oscillator 16, which has the same composition as digital oscillator 7, cumulatively integrates control signal CS at every cycle of clock nfH from waveform shaping circuit 12. Therefore, the oscillation output of digital oscillator 16 becomes a saw-tooth wave in which the frequency is proportional to phase error signal CS.
The oscillation output of digital oscillator 16 is supplied to SIN converter 17 and converted into a sine wave. The output of SIN converter 17 is output to output terminal 18 and is also fed back to phase comparator 14. Thus, a PLL is comprised phase comparator 14, loop filter 15, digital oscillator 16 and SIN converter 17. The burst signal from burst separator circuit 13, that is to say, a demodulated color subcarrier, which is phase synchronized to the color subcarrier, is output at output terminal 18.
Digital oscillator 16 is operated by clock nfH from waveform shaping circuit 12, and its oscillating frequency fsc1 is expressed by the following Equation (2). Here, m2 is the number of integration bits of digital oscillator 16. ##EQU1##
As shown by this Equation (2), apart from the oscillation frequency of digital oscillator 16 being influenced by control signal CS from loop filter 15, it is also influenced by the output signal CH of loop filter 6. Therefore, there is a problem in that, the oscillation frequency of digital oscillator 16 becomes unstable due to the fluctuation of control signal CH in the state at which the relationship between the horizontal synchronization frequency and the color subcarrier frequency rapidly fluctuate (as in VCR and the like).
To take account of this point, a method of demodulating a color subcarrier corresponding to the rapid fluctuation of the horizontal synchronization signal has been disclosed in the specification of U.S. Pat. No. 4,625,232. FIG. 4 is a block diagram showing a prior art color subcarrier demodulation circuit to which this method has been applied.
The point at which FIG. 4 differs from FIG. 1 is that divider 19 has been added between loop filter 15 and digital oscillator 16. Divider 19 is designed to divide control signal CS from loop filter 15 by control signal CH from loop filter 6 and supply the division result to digital oscillator 16 as a control signal.
In this case, oscillation frequency fsc2 of digital oscillator 16 can be expressed by the following Equation (3). ##EQU2##
As shown in Equation (3), oscillation frequency fsc2 of digital oscillator 16 is not affected by control signal CH of loop filter 6. Thus, in FIG. 4, the fluctuation of system clock nfH is compensated. Therefore, in the color subcarrier demodulation circuit in FIG. 4, even if the relationship between the horizontal synchronization frequency and the color subcarrier frequency fluctuates rapidly, a stable demodulated color subcarrier can be demodulated.
However, in the composition of FIG. 4, digital oscillator 16 is controlled by the same divider 19 output throughout 1 horizontal period. Therefore, the output phase error of digital oscillator 16 due to the error of the division result produced by the bit limits of divider 19 accumulates throughout one (1) horizontal period. For instance, in the case of the frequency nfH of the system clock being set at 910 times the horizontal synchronization frequency, the phase error also will be 910 times. For this reason, the operation accuracy of divider 19 is required to be sufficiently high. That is to say, it is necessary to increase the bit number of the control signal supplied to digital oscillator 16. This leads to increasing the scale of the hardware.
In in the prior art color subcarrier demodulation circuit described above, the output phase error of the digital oscillator based on the operation error of the divider accumulates throughout one (1) horizontal period. Therefore, there is a problem in that a high operation accuracy of the divider is required, and it is necessary to increase the scale of the hardware construction.